This invention relates to high density integrated circuit non-volatile memory, and specifically to a method of making a ferroelectric device wherein etching of a bottom electrode is accomplished without damaging the underlying substrate.
One of the most difficult steps in metal/ferro metal oxide semiconductor (MFMOS) ferroelectric memory transistor fabrication is that of etching the bottom electrode. In known NFMOS ferroelectric memory transistor fabrication, the bottom electrode must be selectively etched, without etching through the thin oxide located beneath the bottom electrode, and thereby penetrating the silicon substrate. The oxide located below the bottom electrode may be silicon dioxide, or any other suitable high-k insulator. If the silicon substrate is inadvertently etched, it will be impossible to form source/drain junctions which have adequate connections to the conductive channel of the transistor.
A method of making a ferroelectric memory transistor includes preparing a silicon substrate including forming plural active areas thereon; depositing a layer of gate insulator on the substrate, and depositing a layer of polysilicon over the gate insulator layer; forming a source region, a drain region and a gate electrode; depositing a layer of bottom electrode material and finishing the bottom electrode without damaging the underlying gate insulator and silicon substrate; depositing a layer of ferroelectric material on the bottom electrode, depositing a layer of top electrode material on the ferroelectric material; and finishing the transistor, including passivation oxide deposition, contact hole etching and metalization.
An object of the invention is to provide a production method for single transistor ferroelectric memory device fabrication.
Another object of the invention is to provide a method of forming a bottom electrode in a ferroelectric stack without penetrating the underlying silicon substrate.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.